BBC development board containing a NRF51822-QFAA ARM Cortex-M0 processor with 256KB flash and 16KB RAM.

This page is a work-in-progress whilst I work out how to program this board using a Nordic SDK.

Version 10.0.0 would appear to be the last SDK for just the nRF51 chipset, and 12.3.0 appears to be the last that includes the nRF51.

Here is an overview.

Go to the download page and fetch 12.3.0.

After unzipping the following files are found:

nRF5SDK1230.zip
s130nrf51201.zip
s132nrf52310.zip

`s130nrf51201.zip' is the BT software stack for the nRF51 (known as the Softdevice) and `s130nrf51201.zip' is the SDK for nRF5x.

The Softdevice stack for the nRF52 named `s132nrf52310.zip' is not needed here.

The GNU makefile `components/toolchain/gcc/Makefile.posix' in the SDK sets up GNU_INSTALL_ROOT := /usr/local/gcc-arm-none-eabi-4_9-2015q3 and this toolchain would appear to be an absolute requirement.

This toolchain is available here.

Not sure what to do with this yet.

md5sum s130_nrf51_2.0.1_softdevice.hex
f63d43ae56cada5d5aaa14271fc76681  s130_nrf51_2.0.1_softdevice.hex

Hold down reset and plug board into PC.

Drag J-Link for BBC micro:bit version 1 to MAINTENANCE directory.

Power cycle board and J-Link will become available.

$ /mnt/c/Program\ Files/SEGGER/JLink/JLink.exe
SEGGER J-Link Commander V7.98c (Compiled Aug  7 2024 15:41:14)
DLL version V7.98c, compiled Aug  7 2024 15:40:25

Connecting to J-Link via USB...O.K.
Firmware: J-Link OB-BBC-microbit compiled Nov 16 2022 11:02:58
Hardware version: V1.00
J-Link uptime (since boot): 0d 00h 00m 00s
S/N: 786600064
VTref=3.300V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: NRF51822_XXAA
Type '?' for selection dialog
Device>NRF51822_XXAA
Please specify target interface:
  J) JTAG (Default)
  S) SWD
  T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "NRF51822_XXAA" selected.


Connecting to target via SWD
InitTarget() start
InitTarget() end - Took 12us
Found SW-DP with ID 0x0BB11477
DPIDR: 0x0BB11477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770021)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0000000
CPUID register: 0x410CC200. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ F0000000
[0][0]: E00FF000 CID B105100D PID 000BB471 ROM Table
ROMTbl[1] @ E00FF000
[1][0]: E000E000 CID B105E00D PID 000BB008 SCS
[1][1]: E0001000 CID B105E00D PID 000BB00A DWT
[1][2]: E0002000 CID B105E00D PID 000BB00B FPB
[0][1]: F0002000 CID B105900D PID 000BB9A3 ???
SetupTarget() start
SetupTarget() end - Took 746us
Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M0 identified.
J-Link>

Product homepage

Version 1.5 hardware

Version 1.5 schematic

SEGGER J-Link for micro:bit

MCU product brief

MCU data-sheet

Programming resources