The B-L072Z-LRWAN1 board contains a Murata CMWX1ZZABZ-091 radio module with an Arduino style layout. Inside the radio module are an STM32L072CZ MCU and SEMTECH SX1276.

This development board is designed to deliver LoRa applications based on the ST platform “STM32 LoRaWAN Expansion Package for STM32Cube”.

The STM32Cube package is the only source of information regarding the internal pinout of the module and none of this is divulged by either Murata or ST officially.

The board supports J-Link OB for STM32 to program its flash.

Arduino compatible headers

                PB8    D15  I2C1 SCL
                PB9    D14  I2C1 SDA
                       AVDD
NC                     GND
IOREF       PA5/PB13   D13
NRST            PB14   D12  SPI2 MISO     
3V3             PB15   D11  SPI2 MOSI
5V              PB6    D10  SPI2 CS
GND             PB12   D9
GND             PA9    D8
VIN
                PA8    D7
                PB2    D6
A0 PA0          PB7    D5
A1 PA1/NC       PB5    D4
A2 PA4      PB13/NC    D3   SPI2 SCK
A3 PA4/NC       PA10   D2
A4 PH1/PB9      PA2    D1   USART2 TX
A5 PH0/PB8      PA3    D0   USART2 RX

PB2 B1
PA5 LD2 GREEN
PB5 LD1 GREEN
PB6 LD3 BLUE
PB7 LD4 RED

The device contains a STM32L072CZ MCU, SX1276 LoRa IC, antenna switch and a STSAFE-A100 module (unconfirmed).

The internal connections are documented in the ST source code and the external ones in the user guide.

SPI1 on APB2 alternate function AF0

SPI1 SCK   PB3
SPI1 MISO  PA6
SPI1 MOSI  PA7

GPIO PA15 NSS
GPIO PC0  RESET
GPIO PB4  DIO0
GPIO PB1  DIO1
GPIO PB0  DIO2
GPIO PC13 DIO3
GPIO PA5  DIO4 (enabled with SB26)
GPIO PA4  DIO5 (enabled with SB27)
GPIO PA11 STSAFE RESET (unconfirmed)
GPIO PA12 TXCO VCC
GPIO PA1  ANT SWITCH RX
GPIO PC1  ANT SWITCH TX BOOST
GPIO PC2  ANT SWITCH TX RFO

Two jumpers exist, JP9 and JP10.

JP9

JP9 by default always powers the TXCO (position 2+3), otherwise in position (1+2) the MCU has to control the TXCO VCC on PA12.

JP10

JP10 controls the reset pin on the STSAFE module. In the default position (1+2) the reset is tied to the MCU reset, otherwise in position (2+3) PA11 can reset the STSAFE module (if present).

Datasheet says SIGFOX operation requires the TXCO clock as SYSCLK.

OSC_IN PH0 TXCO OUT (enabled with SB13)

Antenna configuration depends on the mode of operation.

For sleep mode, the pins should be reset before entering, and for receiver and transmitter modes, the pins should be set up prior to entering the mode.

Sleep

Receiver

Transmitter with PABOOST

Transmitter with RFO

TXCO VCC takes 5 ms to start.

Flash the debugger with J-Link for STM32.

This command file just resets the controller state.

USB 777450341
Device STM32L072CZ
SelectInterface SWD
Speed 4000
Reset
Exit

/mnt/c/Program\ Files/SEGGER/JLink/JLink.exe -commandfile b-l072z-lrwan1.reset
SEGGER J-Link Commander V7.82 (Compiled Oct 13 2022 13:39:13)
DLL version V7.82, compiled Oct 13 2022 13:37:46


J-Link Command File read successfully.
Processing script file...
J-Link>USB 777450341
Connecting to J-Link via USB...O.K.
Firmware: J-Link STLink V21 compiled Aug 12 2019 10:29:20
Hardware version: V1.00
J-Link uptime (since boot): N/A (Not supported by this model)
S/N: 777450341
VTref=3.300V
J-Link>Device STM32L072CZ
J-Link>SelectInterface SWD
Selecting SWD as current target interface.
J-Link>Speed 4000
Selecting 4000 kHz as target interface speed
J-Link>Reset
Target connection not established yet but required for command.
Device "STM32L072CZ" selected.


Connecting to target via SWD
InitTarget() start
InitTarget() end
Found SW-DP with ID 0x0BC11477
DPv0 detected
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770031)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0000000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ F0000000
[0][0]: E00FF000 CID B105100D PID 000BB4C0 ROM Table
ROMTbl[1] @ E00FF000
[1][0]: E000E000 CID B105E00D PID 000BB008 SCS
[1][1]: E0001000 CID B105E00D PID 000BB00A DWT
[1][2]: E0002000 CID B105E00D PID 000BB00B FPB
Cortex-M0 identified.
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
J-Link>Exit

Script processing completed.

OnDisconnectTarget() start
OnDisconnectTarget() end

If the dialog contains a message about not being able to connect to the CPU then it's probably because it is sleeping…

...
InitTarget() start
Can not attach to CPU. Trying connect under reset.
Error while checking CPU state.
InitTarget() end
Connect failed. Resetting via Reset pin and trying again.
InitTarget() start
InitTarget() end
Found SW-DP with ID 0x0BC11477
...

Product page

User manual including schematic

ARM mbed product page

Murata CMWX1ZZABZ-091

MCU datasheet

MCU reference manual