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boards:k8048 [2014/12/16 17:32] – darronboards:k8048 [2015/03/22 21:55] (current) – external edit 127.0.0.1
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 ==== Velleman K8048 ==== ==== Velleman K8048 ====
-{{ :boards:16f88.jpg?300}} +<wrap right> 
-== Serial Interface ==+{{:boards:16f88.jpg?200}} 
 +</wrap>
  
-The Velleman programmer board has the following serial interface +The Velleman K8048 is long-standing board that incorporates a serial port programmer and experimenter's I/O section of LEDs and switches.
-characteristics (D-SUB-9): +
- +
-<code> +
- D-SUB-9                                ICSP +
- -------                                ---- +
- OUTPUT +
- 7              RTS -> PGC              5 +
- 4              DTR -> PGD              4 +
- 3              TX  -> !MCLR/VPP        1 +
- INPUT +
- 8              CTS <- PGD              4 +
- OTHER +
- 9 <- 3         RI  <- TX +
-</code>+
  
 Although the interface connects to the serial port, it doesn't utilise Although the interface connects to the serial port, it doesn't utilise
-the RS-232 serial protocol and instead I/O is performed with bit banging.+the RS-232 serial protocol and instead programming is performed using bit-banging.
  
-Data output bits are sent through the DTR line and clocked on the falling 
-edge of RTS. 
  
-The Tx line is utilised to enable the application of the high programming +=== Serial Interface ===
-voltage on !MCLR/VPP and not for sending data bits.+
  
-Data input bits are read from the CTS line using the same clock as for +The bit-bang programmer has the following serial interface 
-output with the data output line taken high for correct circuit operation.+characteristics (D-SUB-9).
  
 <code> <code>
  D-SUB-9  D-SUB-9
- ---------+ -------
  1 2 3 4 5  1 2 3 4 5
   6 7 8 9   6 7 8 9
  
- 1:CD + 1:CD          ICSP 
- 2:Rx + 2:Rx          ---- 
- 3:Tx + 3:Tx      =>  1 !MCLR / VPP 
- 4:DTR + 4:DTR     =>  4 PGD 
- 5:GND+ 5:GND           GND
  6:DSR  6:DSR
- 7:RTS + 7:RTS     =>  5 PGC 
- 8:CTS+ 8:CTS     <=  4 PGD
  9:RI  9:RI
 </code> </code>
 +
 +Data output bits are sent through the DTR line and clocked on the falling
 +edge of RTS.
 +
 +The Tx line is utilised to enable the application of the high programming
 +voltage on !MCLR/VPP and not for sending data bits.
 +
 +Data input bits are read from the CTS line using the same clock as for
 +output with the data output line taken high for correct circuit operation.
  
  
-== Socket Cross Reference ==+=== Socket Cross Reference ===
  
 <code> <code>
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 </code> </code>
  
-== ICSP ==+=== ICSP ===
  
 <code> <code>
- SK3 is an ICSP port, the pins are arranged as follows: + SK3
- +
- ICSP+
  ---------  ---------
  5 4 3 2 1  5 4 3 2 1
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  4:PGD  4:PGD
  5:PGC  5:PGC
-</code> 
  
-<code> + Voltage levels (No chip installed, no D-SUB-9 connection) 
- ICSP voltage levels (No chip installed, no D-SUB-9 connection) + ---------------------------------------------------------
- --------------------------------------------------------------+
  
  Switch set to RUN.  Switch set to RUN.
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  5:PGC          5V  5:PGC          5V
 </code> </code>
 +
 +=== Resources ===
 +[[http://www.velleman.eu/products/view/?id=350903|Velleman K8048]]
 +
 +