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boards:h755ziq [2024/10/26 01:05] – [RAM] darronboards:h755ziq [2024/11/07 22:41] (current) – darron
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 </wrap> </wrap>
  
-Dual core MCU with Cortex-M7 at 480MHz and Cortex-M4 at 240MHz with 2MB Flash and 1MB RAM.+Dual core STM32H755ZI MCU with Cortex-M7 at 480MHz and Cortex-M4 at 240MHz with 2MB Flash and 1MB RAM.
  
 ===Pinout=== ===Pinout===
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 [[https://www.st.com/resource/en/errata_sheet/es0445-stm32h745xig-stm32h755xi-stm32h747xig-stm32h757xi-device-errata-stmicroelectronics.pdf|MCU errata]] [[https://www.st.com/resource/en/errata_sheet/es0445-stm32h745xig-stm32h755xi-stm32h747xig-stm32h757xi-device-errata-stmicroelectronics.pdf|MCU errata]]
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 [[https://www.st.com/resource/en/application_note/an5617-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf|STM32 dual core IPC]] [[https://www.st.com/resource/en/application_note/an5617-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf|STM32 dual core IPC]]
 +
 +[[https://web.archive.org/web/20200217044809/http://blog.atollic.com/using-gnu-gcc-on-arm-cortex-devices-placing-code-and-data-on-special-memory-addresses-using-the-gnu-ld-linker|GNU ld linker]]
 +
 +[[https://www.st.com/resource/en/application_note/dm00272912-managing-memory-protection-unit-in-stm32-mcus-stmicroelectronics.pdf|STM32 ARM MPU]]
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 +[[https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-access-permission-attributes?lang=en|ARM MPU permissions]]