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boards:h755ziq [2024/10/26 00:32] – [Pinout] darronboards:h755ziq [2025/02/05 05:30] (current) – [NUCLEO-H755ZI-Q] darron
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 </wrap> </wrap>
  
-Dual core MCU with Cortex-M7 at 480MHz and Cortex-M4 at 240MHz with 2MB Flash and 1MB RAM.+Dual core STM32H755ZI MCU with Cortex-M7 at 480MHz and Cortex-M4 at 240MHz with 2MB Flash and 1MB RAM.
  
 +
 +The Q suffix indicates that this processor and board contains a SMPS.
 +
 +The user manual explains that the SMPS must be enabled in
 +firmware otherwise there will be no connection to the device over ST-LINK.
 ===Pinout=== ===Pinout===
  
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 ===RAM=== ===RAM===
  
-<code> +^Address ^Type^Size^Alias^ 
-0x38800000 .. 0x38800FFF BACKUP SRAM +|0x00000000 .. 0x0000FFFF|ITCM (CM7) |64KB | | 
- +|0x20000000 .. 0x2001FFFF|DTCM (CM7) |128KB| | 
-0x38000000 .. 0x3800FFFF SRAM4 +|0x24000000 .. 0x2407FFFF|AXI SRAM |512KB| | 
- +|0x30000000 .. 0x3001FFFF|SRAM1    |128KB|0x10000000 .. 0x1001FFFF| 
-0x30040000 .. 0x30047FFF SRAM3 +|0x30020000 .. 0x3003FFFF|SRAM2    |128KB|0x10020000 .. 0x1003FFFF| 
- +|0x30040000 .. 0x30047FFF|SRAM3    |32KB |0x10040000 .. 0x10047FFF| 
-0x30020000 .. 0x3003FFFF SRAM2 +|0x38000000 .. 0x3800FFFF|SRAM4    |64KB | 
- +|0x38800000 .. 0x38800FFF|BACKUP SRAM| 4KB|
-0x30000000 .. 0x3001FFFF SRAM1 +
- +
-0x24000000 .. 0x2407FFFF AXI SRAM +
- +
-0x20000000 .. 0x2001FFFF DTCM (*) +
- +
-(*) CM7 only +
-</code>+
  
 ===Resources=== ===Resources===
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 [[https://www.st.com/resource/en/errata_sheet/es0445-stm32h745xig-stm32h755xi-stm32h747xig-stm32h757xi-device-errata-stmicroelectronics.pdf|MCU errata]] [[https://www.st.com/resource/en/errata_sheet/es0445-stm32h745xig-stm32h755xi-stm32h747xig-stm32h757xi-device-errata-stmicroelectronics.pdf|MCU errata]]
 +
  
  
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 [[https://www.st.com/resource/en/application_note/an5617-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf|STM32 dual core IPC]] [[https://www.st.com/resource/en/application_note/an5617-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf|STM32 dual core IPC]]
 +
 +[[https://web.archive.org/web/20200217044809/http://blog.atollic.com/using-gnu-gcc-on-arm-cortex-devices-placing-code-and-data-on-special-memory-addresses-using-the-gnu-ld-linker|GNU ld linker]]
 +
 +[[https://www.st.com/resource/en/application_note/dm00272912-managing-memory-protection-unit-in-stm32-mcus-stmicroelectronics.pdf|STM32 ARM MPU]]
 +
 +[[https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-access-permission-attributes?lang=en|ARM MPU permissions]]