Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| projects:icspio [2015/01/11 17:41] – [Demo] darron | projects:icspio [2017/01/12 22:44] (current) – external edit 127.0.0.1 | ||
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| Line 9: | Line 9: | ||
| the Velleman K8048. | the Velleman K8048. | ||
| - | ICSP I/O was not designed a replacement for more established | + | ICSP I/O was not designed |
| and more reliable protocols but it can be used for prototyping. | and more reliable protocols but it can be used for prototyping. | ||
| Line 79: | Line 79: | ||
| PGD is used for data I/O with even parity and PGC for clock synchronisation. | PGD is used for data I/O with even parity and PGC for clock synchronisation. | ||
| PGC is unidirectional and is only controlled by the master (host), this is the | PGC is unidirectional and is only controlled by the master (host), this is the | ||
| - | slave. The interface may or not be inverted but this is catered for by the | + | slave. The interface may or not be inverted but this is catered for by |
| - | k8048 Microchip PIC programmer | + | [[: |
| - | Data is setup on the master prior to a clock low to high transition and setup | + | Data is set up on the master prior to a clock low to high transition and set up |
| on the slave after a clock low to high transition. Data is read after a clock | on the slave after a clock low to high transition. Data is read after a clock | ||
| high to low transition on both master and slave. | high to low transition on both master and slave. | ||
