Differences
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boards:wio-e5 [2022/12/29 12:10] darron |
boards:wio-e5 [2022/12/31 19:18] (current) darron [STM32WLE5JC] |
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| Line 13: | Line 13: | ||
| The MCU does not contain a FPU, only the mandatory DSP for m4 | The MCU does not contain a FPU, only the mandatory DSP for m4 | ||
| cores, but it does have an embedded radio, it appears to be an SX1262. | cores, but it does have an embedded radio, it appears to be an SX1262. | ||
| + | |||
| ===STM32WLE5JC=== | ===STM32WLE5JC=== | ||
| - | RAM is in two 32K banks, which may be addressed | + | RAM is in two 32K banks, which may be addressed separately or contiguously. The |
| second bank has extended features when used separately. | second bank has extended features when used separately. | ||
| Line 25: | Line 26: | ||
| LoRa | LoRa | ||
| </ | </ | ||
| + | |||
| + | There is a warning in the reference manual on page 185 of RM0461 Rev 5: | ||
| + | |||
| + | "The SMPS needs a clock to be functional. If for any reason this clock stops, | ||
| + | the device may be destroyed." | ||
| + | |||
| + | I probably would not have bothered with this board had I read the above warning beforehand. | ||
| + | Who designs a MCU that can self destruct if a bit doesn' | ||
| + | |||
| ===Test=== | ===Test=== | ||
| Line 190: | Line 200: | ||
| ===Clock=== | ===Clock=== | ||
| - | HSE 32MHz TCXO | + | On reset the MCU uses the MSI clock at 4 MHz. |
| + | |||
| + | ==HSE== | ||
| + | |||
| + | 32MHz TCXO | ||
| < | < | ||
| Line 196: | Line 210: | ||
| </ | </ | ||
| - | LSE 32.768KHz | + | ==LSE== |
| + | 32.768KHz | ||
| ===Antenna=== | ===Antenna=== | ||
| Line 243: | Line 258: | ||
| [[https:// | [[https:// | ||
| + | [[https:// | ||
