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boards:wio-e5 [2022/12/29 00:10]
darron [Wio-E5] 		boards:wio-e5 [2022/12/31 19:18] (current)
darron [STM32WLE5JC]
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 {{boards:lora-e5-block.jpg?100}} {{boards:subghz.jpg?100}} {{boards:lora-e5-block.jpg?100}} {{boards:subghz.jpg?100}}
 \\ \\
-{{boards:wio-e5-pinout.png?100}}+{{boards:wio-e5-pinout.png?100}} {{boards:lora-e5-schematic.jpg?100}}
 </wrap> </wrap>
  
-STM32WLE5JC+This board has a package containing a STM32WLE5JC cortex-m4 microcontroller at 48 MHz. 
 + 
 +The MCU does not contain a FPU, only the mandatory DSP for m4 
 +cores, but it does have an embedded radio, it appears to be an SX1262. 
 + 
 + 
 +===STM32WLE5JC=== 
 + 
 +RAM is in two 32K banks, which may be addressed separately or contiguously. The 
 +second bank has extended features when used separately.
  
 <code> <code>
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 LoRa LoRa
 </code> </code>
 +
 +There is a warning in the reference manual on page 185 of RM0461 Rev 5:
 +
 +"The SMPS needs a clock to be functional. If for any reason this clock stops,
 +the device may be destroyed."
 +
 +I probably would not have bothered with this board had I read the above warning beforehand.
 +Who designs a MCU that can self destruct if a bit doesn't get set in error?
 +
  
 ===Test=== ===Test===
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 To program the board connect with a [[tools:segger|J-Link EDU Mini]]. This To program the board connect with a [[tools:segger|J-Link EDU Mini]]. This
-will require an adapter or some sort.+will require an adapter of some sort.
  
 Warning: This process will erase the write protected firmware and this Warning: This process will erase the write protected firmware and this
 is non-recoverable. is non-recoverable.
 +
 +NB when removing protection, the device will need to be power cycled afterwards.
  
 <code> <code>
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   Zone: Default Description: Default access mode   Zone: Default Description: Default access mode
 Cortex-M4 identified. Cortex-M4 identified.
-J-Link>+J-Link>mem32 0x8000000 0x20 
 +08000000 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000010 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000020 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000030 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000040 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000050 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000060 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 
 +08000070 = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
 </code> </code>
 ===Erase=== ===Erase===
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 Connecting to the board using JLinkExe will remove protection and erase Connecting to the board using JLinkExe will remove protection and erase
 the firmware but this can also be done using a standalone tool. the firmware but this can also be done using a standalone tool.
 +
 +NB when removing protection, the device will need to be power cycled afterwards.
  
 <code> <code>
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 ===Clock=== ===Clock===
  
-HSE 32MHz TCXO+On reset the MCU uses the MSI clock at 4 MHz. 
 + 
 +==HSE== 
 + 
 +32MHz TCXO
  
 <code> <code>
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 </code> </code>
  
-LSE 32.768KHz+==LSE==
  
 +32.768KHz
 ===Antenna=== ===Antenna===
  
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 [[https://www.st.com/resource/en/application_note/an5457-rf-matching-network-design-guide-for-stm32wl-series-stmicroelectronics.pdf|MCU RF design guide]] [[https://www.st.com/resource/en/application_note/an5457-rf-matching-network-design-guide-for-stm32wl-series-stmicroelectronics.pdf|MCU RF design guide]]
  
 +[[https://www.farnell.com/datasheets/2829356.pdf|SX1262 datasheet]]