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boards:pico [2022/11/08 17:51] darron |
boards:pico [2022/11/12 15:27] (current) darron [Tools] |
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+ | ====Raspberry Pi PICO==== | ||
<wrap right> | <wrap right> | ||
- | {{: | + | {{: |
\\ \\ | \\ \\ | ||
- | {{: | + | {{: |
</ | </ | ||
+ | Dual core Arm Cortex M0 microcontroller designed to run MicroPython. | ||
- | https:// | + | There are four varieties of this board produced by RPi. The differences |
+ | are whether they come pre-installed with header pins and a debug socket | ||
+ | and if they have a WiFi adapter on board. | ||
+ | ===Tools=== | ||
- | https://github.com/ | + | Read this [[https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf|guide]]. Within |
+ | is the setup procedure for development tools is as follows: | ||
+ | < | ||
+ | wget https:// | ||
+ | sh pico_setup.sh | ||
+ | </ | ||
+ | |||
+ | This will install the ARM compiler, OpenOCD, the SDK, examples, and various other things. | ||
+ | |||
+ | OpenOCD is built from source with the following options: | ||
+ | < | ||
+ | ./configure --enable-ftdi --enable-sysfsgpio --enable-bcm2835gpio --enable-picoprobe | ||
+ | </ | ||
+ | ===J-Link=== | ||
+ | |||
+ | <wrap right> | ||
+ | {{: | ||
+ | </ | ||
+ | |||
+ | Segger J-Link can be use to interact with the PICO via the debug port. | ||
+ | |||
+ | ==CORE 0== | ||
+ | |||
+ | < | ||
+ | echo " | ||
+ | SEGGER J-Link Commander V7.82a (Compiled Oct 31 2022 11:25:49) | ||
+ | DLL version V7.82a, compiled Oct 31 2022 11:25:22 | ||
+ | |||
+ | Connecting to J-Link via USB...O.K. | ||
+ | Firmware: J-Link EDU Mini V1 compiled Oct 21 2022 11:17:52 | ||
+ | Hardware version: V1.00 | ||
+ | J-Link uptime (since boot): 0d 00h 09m 41s | ||
+ | S/N: 801011752 | ||
+ | License(s): FlashBP, GDB | ||
+ | USB speed mode: Full speed (12 MBit/s) | ||
+ | VTref=3.259V | ||
+ | Device " | ||
+ | |||
+ | |||
+ | Connecting to target via SWD | ||
+ | ConfigTargetSettings() start | ||
+ | J-Link script: ConfigTargetSettings() | ||
+ | ConfigTargetSettings() end | ||
+ | Found SW-DP with ID 0x0BC12477 | ||
+ | DPIDR: 0x0BC12477 | ||
+ | CoreSight SoC-400 or earlier | ||
+ | Scanning AP map to find all available APs | ||
+ | AP[1]: Stopped AP scan as end of AP map has been reached | ||
+ | AP[0]: AHB-AP (IDR: 0x04770031) | ||
+ | Iterating through AP map to find AHB-AP to use | ||
+ | AP[0]: Core found | ||
+ | AP[0]: AHB-AP ROM base: 0xE00FF000 | ||
+ | CPUID register: 0x410CC601. Implementer code: 0x41 (ARM) | ||
+ | Found Cortex-M0 r0p1, Little endian. | ||
+ | FPUnit: 4 code (BP) slots and 0 literal slots | ||
+ | CoreSight components: | ||
+ | ROMTbl[0] @ E00FF000 | ||
+ | [0][0]: E000E000 CID B105E00D PID 000BB008 SCS | ||
+ | [0][1]: E0001000 CID B105E00D PID 000BB00A DWT | ||
+ | [0][2]: E0002000 CID B105E00D PID 000BB00B FPB | ||
+ | Cortex-M0 identified. | ||
+ | </ | ||
+ | |||
+ | ==CORE 1== | ||
+ | |||
+ | < | ||
+ | echo " | ||
+ | SEGGER J-Link Commander V7.82a (Compiled Oct 31 2022 11:25:49) | ||
+ | DLL version V7.82a, compiled Oct 31 2022 11:25:22 | ||
+ | |||
+ | Connecting to J-Link via USB...O.K. | ||
+ | Firmware: J-Link EDU Mini V1 compiled Oct 21 2022 11:17:52 | ||
+ | Hardware version: V1.00 | ||
+ | J-Link uptime (since boot): 0d 00h 09m 48s | ||
+ | S/N: 801011752 | ||
+ | License(s): FlashBP, GDB | ||
+ | USB speed mode: Full speed (12 MBit/s) | ||
+ | VTref=3.260V | ||
+ | Device " | ||
+ | |||
+ | |||
+ | Connecting to target via SWD | ||
+ | ConfigTargetSettings() start | ||
+ | J-Link script: ConfigTargetSettings() | ||
+ | ConfigTargetSettings() end | ||
+ | Found SW-DP with ID 0x0BC12477 | ||
+ | DPIDR: 0x0BC12477 | ||
+ | CoreSight SoC-400 or earlier | ||
+ | Scanning AP map to find all available APs | ||
+ | AP[1]: Stopped AP scan as end of AP map has been reached | ||
+ | AP[0]: AHB-AP (IDR: 0x04770031) | ||
+ | Iterating through AP map to find AHB-AP to use | ||
+ | AP[0]: Core found | ||
+ | AP[0]: AHB-AP ROM base: 0xE00FF000 | ||
+ | CPUID register: 0x410CC601. Implementer code: 0x41 (ARM) | ||
+ | Found Cortex-M0 r0p1, Little endian. | ||
+ | FPUnit: 4 code (BP) slots and 0 literal slots | ||
+ | CoreSight components: | ||
+ | ROMTbl[0] @ E00FF000 | ||
+ | [0][0]: E000E000 CID B105E00D PID 000BB008 SCS | ||
+ | [0][1]: E0001000 CID B105E00D PID 000BB00A DWT | ||
+ | [0][2]: E0002000 CID B105E00D PID 000BB00B FPB | ||
+ | Cortex-M0 identified. | ||
+ | </ | ||
+ | |||
+ | ===Resources=== | ||
+ | |||
+ | https:// | ||
+ | |||
+ | https:// | ||
https:// | https:// |