====NUCLEO-H755ZI-Q====

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Dual core STM32H755ZI MCU with Cortex-M7 at 480MHz and Cortex-M4 at 240MHz with 2MB Flash and 1MB RAM.


The Q suffix indicates that this processor and board contains a SMPS.

The user manual explains that the SMPS must be enabled in
firmware otherwise there will no connection to the device over ST-LINK.
===Pinout===

<code>
PB6 USART1_TX ARDUINO D1 TX
PB7 USART1_RX ARDUINO D0 RX

PD8 USART3_TX VCP_TX
PD9 USART3_RX VCP_RX

LED
PB0  LD1 GREEN
PE1  LD2 YELLOW
PB14 LD3 RED

OSC32
X3 NX3215SA 32.768KHz
</code>

===RAM===

^Address ^Type^Size^Alias^
|0x00000000 .. 0x0000FFFF|ITCM (CM7) |64KB | |
|0x20000000 .. 0x2001FFFF|DTCM (CM7) |128KB| |
|0x24000000 .. 0x2407FFFF|AXI SRAM |512KB| |
|0x30000000 .. 0x3001FFFF|SRAM1    |128KB|0x10000000 .. 0x1001FFFF|
|0x30020000 .. 0x3003FFFF|SRAM2    |128KB|0x10020000 .. 0x1003FFFF|
|0x30040000 .. 0x30047FFF|SRAM3    |32KB |0x10040000 .. 0x10047FFF|
|0x38000000 .. 0x3800FFFF|SRAM4    |64KB |
|0x38800000 .. 0x38800FFF|BACKUP SRAM| 4KB|

===Resources===

[[https://www.st.com/en/evaluation-tools/nucleo-h755zi-q.html|Product page]]

[[https://www.st.com/resource/en/user_manual/um2408-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf|User manual]]

[[https://www.st.com/resource/en/schematic_pack/mb1363-h755ziq-d01_schematic.pdf|Schematic]]

[[https://www.st.com/en/microcontrollers-microprocessors/stm32h755zi.html|MCU product page]]

[[https://www.st.com/resource/en/datasheet/stm32h755zi.pdf|MCU data-sheet]]

[[https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf|MCU reference manual]]

[[https://www.st.com/resource/en/errata_sheet/es0445-stm32h745xig-stm32h755xi-stm32h747xig-stm32h757xi-device-errata-stmicroelectronics.pdf|MCU errata]]



[[https://www.st.com/resource/en/application_note/an5557-stm32h745755-and-stm32h747757-lines-dualcore-architecture-stmicroelectronics.pdf|STM32 dual core architecture]]

[[https://www.st.com/resource/en/application_note/an5617-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf|STM32 dual core IPC]]

[[https://web.archive.org/web/20200217044809/http://blog.atollic.com/using-gnu-gcc-on-arm-cortex-devices-placing-code-and-data-on-special-memory-addresses-using-the-gnu-ld-linker|GNU ld linker]]

[[https://www.st.com/resource/en/application_note/dm00272912-managing-memory-protection-unit-in-stm32-mcus-stmicroelectronics.pdf|STM32 ARM MPU]]

[[https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-access-permission-attributes?lang=en|ARM MPU permissions]]